Semiconductor device and manufacturing method thereof

ABSTRACT

In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

This application claims priority to prior application JP 2004-88308, thedisclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and amanufacturing method thereof and, particularly, to a semiconductordevice and a manufacturing method thereof which can preventcharacteristic deterioration due to metallic contamination which occursin a backside grinding process and a package assembly process performedafter formation of desired devices, wiring, and insulating film on amain surface of a semiconductor substrate.

2. Description of the Related Art

A conventional semiconductor device is fabricated as follows, inaccordance with a process flowchart shown in FIG. 1, electronic devices3, wiring 4, an interlayer Insulating film 5, and the like, are formedon a surface of a silicon substrate 1. Thereafter a substrate's backside6 is grinded so that the substrate can have a desired thickness.Subsequently, the substrate is diced into chips and, in a TSOP assemblyprocess, a lead frame with LOC tape and a chip are bonded through theLOC tape. Then, after wire bonding, resin sealing is carried out.

As described In Japanese Patent Application Publication (JP-A) No.H1-67922, in a conventional semiconductor device, desired electronicdevices, wiring, an insulating film and the like are formed after agettering layer for counteracting metallic contamination, which isintroduced in formation processes, is formed on a substrate's backside.

A conventional semiconductor device has the following drawbacks. When abackside is grinded as shown in FIG. 2, the grinded surface receivesgrinding damages such as dislocations 7 and damages (cracks) 8 andmetallic contamination is also introduced into the areas of grindingdamages. Moreover, in the subsequent dicing process, dicing damages,which are similar to grinding damages, are introduced into the sidesurfaces of chips and metallic contamination is also introduced into theside surfaces of the chips.

In addition, after bonding of a lead frame and chips through the LOCtape, the chips in the above-mentioned state are then exposed to thermalprocess through baking (30 minutes at 150 degrees centigrade, and 90minutes at 230 degrees centigrade) as well as resin sealing (severaltens of minutes at 180 degrees centigrade). Therefore, the metalintroduced during the grinding or dicing process is affected by thethermal process in the assembly processes and the metal attached to thegrinded surface reaches an electronic device formed on the main surfaceof the substrate. For example, in the foregoing TSOP assembly process,in the case of resin sealing, thermal process of several ten minutes at180 degrees centigrade is applied to the chips. Therefore, where metalsuch as copper or the like is attached to a grinded surface, a diffusionlength thereof within the substrate (silicon) becomes several 100 μm. Inaddition, since the thickness of the chip after the backside grinding isalso several 100 μm, the metal can easily reach an electronic deviceformed on the substrate's main surface.

As described above, once a contaminating metal reaches an electronicdevice on a main surface of a substrate, various problems becomeapparent. For example, when a contaminating metal reaches the depletionlayer of a source/drain junction, it leads to the formation of surfacestate and thus causes the generation of Junction leakage current.Furthermore, if a contaminating metal reaches a gate insulating film,insulating film leakage current increases. Because of such increases inthe leakage current, characteristics of an electronic device aredeteriorated. The above-mentioned problem has been increasingly seriousparticularly in recent years as a multi-chip package, wherein chips witha reduced thickness of about 100 μm are stacked, has beencommercialized.

A backside gettering layer formed in a conventional semiconductor devicedescribed in Japanese Patent Application Publication No. H1-67922 has agettering effect against metallic contamination introduced in formationprocesses of electronic devices and the like. However, since a backsideof a substrate in a wafer state is grinded to have a desired thicknessbefore assembled onto a package assembly, the gettering layer is removedby the grinding. Hence, the gettering layer loses its getteringcapability against metallic contamination introduced in the backsidegrinding and package assembly. Because the backside gettering layer isremoved by backside grinding, it is not feasible to preventcharacteristic deterioration caused by metallic contamination introducedafter the backside grinding.

Nevertheless, since the backside receives grinding damages caused by thebackside grinding, which produces gettering capability remains, albeitonly slightly. Yet, the gettering capability produced by a grindingdamage layer is not sufficient and is not able to suppress theabove-described characteristic deterioration. Particularly, in recentyears, adverse effects of metal contamination from a backside towards amain surface have been significant more than ever since a chip thicknessin a multi chip package and the like after backside grinding has beenreduced to around 100 μm.

SUMMARY OF THE INVENTION

An object of the present invention is to resolve these problems andprovide a semiconductor device and a manufacturing method thereof whichcan prevent characteristic deterioration due to metallic contaminationwhich occurs during backside grinding, dicing and package assembly.

In the present invention, a thermal treatment is applied to a backsidegrinding damage layer or a dicing damage layer in an atmospherecontaining an impurity, thus forming a gettering layer to capture acontaminating metal. Furthermore, by using a material containing lesscontaminating metal and cleaning a contaminating metal away,concentration of the contaminating metal is reduced, thus obtaining asemiconductor device manufacturing method and a semiconductor devicewhich can prevent characteristic deterioration due to metalliccontamination which occurs in backside grinding and package assembly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an assembly process flowchart of conventional device.

FIG. 2 is a view showing an image of backside grinding.

FIG. 3 is a view showing an image of a grinded surface.

FIG. 4 is an assembly process flowchart in embodiment 1.

FIG. 5 is a view showing laser beam irradiation in embodiment 1.

FIG. 6 is a graph showing laser power dependence of maximum backsidetemperature in embodiment 1.

FIG. 7 is a graph showing depth dependence of substrate temperature inembodiment 1.

FIG. 8 is a graph showing distribution of oxygen concentration inembodiment 1.

FIG. 9 is a view showing an Image of a grinded surface after thermaltreatment in embodiment 1.

FIG. 10 is a view showing a method of heating a backside of a chip inembodiment 1.

FIG. 11 is a graph showing characteristic deterioration rates inembodiment 1.

FIG. 12 is an assembly process flowchart in embodiment 2.

FIG. 13 is a graph showing distribution of a copper concentration inembodiment 2.

FIG. 14 is a graph showing characteristic deterioration rates inembodiment 2.

FIG. 15 is an assembly process flowchart of embodiment 3.

FIG. 16 is a graph showing a characteristic deterioration rate inembodiment 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A semiconductor device and a manufacturing method thereof are describedbelow in detail with reference to the drawings.

Embodiment 1

Embodiments of the present invention are detailed using TSOP assembly ofa semiconductor device shown in FIGS. 4 to 11 as examples. An isassembly flowchart of the present invention has additional processes oflaser beam irradiation for the backside of a wafer and pressing a hotmaterial to a chip's backside.

First of all, as shown in the assembly flowchart of FIG. 4, the surfaceof a silicon wafer, on which semiconductor devices have been fabricatedin a normal method, was protected with a protection sheet, and thebackside of the wafer was grinded. During this grinding process, thefirst rough grinding was performed at roughness of about #300 until thewafer thickness becomes about between 750 μm and 300 μm, and finishinggrinding was then performed at roughness of about #2000 until the waferthickness becomes 280 μm. Thereafter, the protection sheet on thesurface is removed and washed with water in order to remove dustsattached to the grinded surface during the grinding.

As shown in FIG. 6, in order to form a gettering layer, the wafer'sbackside 11 is irradiated with a laser beam 12 while the backside 11 isexposed to an atmosphere containing oxygen. The laser beam was a linearbeam with a beam diameter of 0.2 mm and laser power ranging from 9 W to18 W. Irradiation of this beam is carried out at a scanning rate of 1mm/s. At this time, as shown in FIG. 6, maximum temperature of thebackside can be controlled by power and is preferably between 300degrees centigrade for about 10 seconds and 900 degrees centigrade forabout 0.01 seconds. The atmosphere containing oxygen may be anatmosphere containing oxygen only, or air, as long as it contains atleast 1% of oxygen so that oxygen is supplied to the substrate.

In this embodiment, maximum temperature is set to 800 degreescentigrade. Effective thermal treatment time is 0.1 seconds. By thisthermal treatment, sufficient oxygen was supplied to dislocations andscratches (cracks) generated during backside grinding, thus increasinggettering capability. As shown in FIG. 8, an oxygen concentration ofconventional device without thermal treatment shows a liner decline from2×10²¹/cm³ near the backside to 2×10¹⁸/cm³ at an average depth of agrinding damaged layer.

An oxygen concentration of the present invention was 2×10²¹/cm³ near thebackside, but a high concentration area between 10²⁰/cm³ and 10²¹/cm³had oxygen distribution similar to that of conventional device butoxygen diffusion is slightly more advanced. The next concentration areahas an impurity-diffused region between 10¹⁹ and 10²⁰/cm³, and this areahas a very moderate gradient because of the thermal treatment of thepresent invention. In an area deeper than this, the concentrationsuddenly drops to an original oxygen concentration of a siliconsubstrate.

The concentration distribution in the present invention was the oneobtained by adding the distribution of further introduced impurity tothe conventional concentration distribution. The impurity diffusedregion having a very gentle concentration gradient is where impurity isintroduced by thermal treatment for impurity introduction and is calleda gettering impurity introduced region. In this embodiment, theconcentration in the gettering impurity introduced region was 2×10¹⁹/cm³or higher, about 10 times that of conventional device. The highertreatment temperature or the longer treatment time, the higher theconcentration becomes. The region between the backside and an areahaving a concentration of 2×10¹⁹/cm³ or higher, and the getteringimpurity introduced region acts as a main gettering layer.

On the damaged layer of the grinded backside, an impurity is easilydiffused along dislocations, defects, and cracks and the concentrationthereof will become 2×10¹⁹ cm³, equal to or higher than the solidsolubility. However, in a normal silicon substrate region deeper thanthe grinding damaged layer, it is impossible for an impurity to diffusewith a concentration equal to or higher than the solid solubility, andthe concentration thus drops sharply to an original oxygen concentrationof the silicon substrate. Therefore, it can be said that the depth of agettering layer and an average depth of a grinding damaged layer formedduring backside grinding are virtually the same. Moreover, a getteringlayer has an oxygen concentration equal to or higher than the maximumsolid solubility (for example, 2×10¹⁸/cm³ for oxygen), and oxygen ispresent in a form of an oxide film, an incomplete oxide film (Si—O) oroxygen precipitation, serving as a gettering center againstcontamination metal.

Therefore, in comparison with conventional device, this example had amuch higher concentration of oxygen because of an addition of agettering impurity introduced region, and the damaged layer generatescrystal defects, dislocations and stacking faults, which then become agettering layer where sufficient trapping sites for fixing metalliccontamination were formed. The grinding damaged layer means a regionwhere defects and scratches (cracks) are generated. The average depth ofthe grinding damaged layer means a depth of a region where at least anyof the defects and scratches (cracks) are continuously generated and thedefects and damages (cracks) adjoin each other within a distanceequivalent to a size of each of defects and scratches (cracks).

Note that, in the grinding damaged layer, the concentration distributionbecomes the highest near the backside and gets gradually lower in adeeper area from the backside (an area closer to the electronic deviceside on the surface). Normally, the concentration distribution can bemeasured by the secondary-ion mass spectrometry. However, with thismethod, analysis results will be abnormal for an area between thebackside and the depth of 10 nm as such area is effected by interfaces.Therefore, the concentration of the above grinding damaged layer nearthe backside is indicated as a concentration analyzed at a depth of 10nm or more from the backside where no effects were imposed by theinterfaces. Further, the concentration within the grinding damaged layerindicates a concentration of 2×10¹⁸/cm³ or higher, the maximum solidsolubility of oxygen within silicon crystal.

FIG. 9 shows an image of a backside state after the thermal treatment.By conducting the thermal treatment of the grinding damaged layer in anatmosphere containing oxygen allows interfaces of the scratches 8 in thedamaged layer to be oxidized, forming oxide films 9, and oxygen to beprecipitated 10 and crystal defects such as stacking faults were allowedto be occurred in dislocations 7 on the damaged layer. The oxide film 9,oxygen precipitation 10 and crystal defects fixed contaminating metalsand acted as trapping sites of the contaminating metals. In the grindingdamaged layer, oxygen soaks through the damaged layer along the defectsand scratches (cracks). Therefore, the depth of the damaged layer and adepth of a region where highly concentrated oxygen is distributed arevirtually the same. Therefore, the average depth of the grinding damagedlayer and the depth of the gettering layer are the same.

A temperature distribution from the backside is as shown in FIG. 7, andthe temperature of the substrate main surface was about 150 degreescentigrade. Since the substrate main surface received a low temperaturetreatment only, there is no characteristic change of electronic devicesat all. However, attentions need to be paid to the fact that thermaltreatment for several lens of seconds at 300 degrees centigrade or overmay cause desorption of hydrogen which terminates defects. As thehydrogen desorption develops, joint leakage current may increase and athreshold value of transistors may change, resulting in characteristicchanges. Therefore, it is necessary to select irradiation conditions oflaser beam which maintain temperature of substrate surface at 300degrees centigrade or lower.

Next, the wafer is diced into chips in the state that a protection sheetfor dicing was adhered to the backside of the wafer. At this time,temperature of adhesion was set at 150 degrees centigrade. Side surfacesof diced chips were mechanically damaged, which means that dicingdamages, similar to grinding damages on the backsides of the chips, wereformed on side surfaces of the chips.

After completion of dicing, a second gettering layer was formed. Asshown in FIG. 10, thermal treatment of the chips was carried out at hightemperature of 300 degrees centigrade for about 10 seconds and 900degrees centigrade for about 0.01 seconds in an oxygen-containingatmosphere. In this embodiment, the backside of the chip 15 was pressedfor 0.5 seconds against quartz 14 coating a piece of metal 13 heated to600 degrees centigrade. This allows gettering capability on the backsideto further enhance and, at the same time, gettering layers were formedon the damaged layers on diced surfaces on the side of the chips as theywere provided with oxygen and subjected to the thermal treatment. Byforming gettering layers on chips after dicing, the surfaces of thechips are protected by passivation layers and both backsides and sidesurfaces of the chips are provided with gettering layers and thusgettering capabilities against metallic contamination, preventingcharacteristic deterioration.

At this time, the oxygen concentration of the backside damaged layernear the back side was 2×10²¹/cm³, and the same at the average depth ofthe backside damaged layer was 4×10¹⁹/cm³, about 20 times theconcentration of 2×10¹⁸/cm³ without sufficient oxygen supply. The oxygendistribution on the side surface of the chip is 2×10²¹/cm³ near theinterface and the same at the average depth of the dicing damaged layerwas 2×10¹⁹/cm³.

As shown in FIG. 8, as for the average depth of the grinding damagedlayer, the concentration of the gettering layer on the backside wasdoubled to 4×10¹⁹/cm³ as the concentration of the second gettering layeris superimposed on that of the first gettering layer, whereas theconcentration of the gettering layer on the side surface of the chip was2×10¹⁹/cm³, which was the concentration of the second gettering layeronly. After the first gettering, the concentration becomes 2×10¹⁹ cm³(see FIG. 8(a), 8(b) and 8(g)), and the concentration becomes higherafter the second gettering to 4×10¹⁹/cm³ (see FIG. 8(c)). In addition,higher the treatment temperature and longer the treatment time become,provided higher concentration. The concentration near the backside wasalmost consistent due to the foregoing problem of measurement error. Asdescribed above, it is evident that higher treatment temperature andhigher treatment time can form a gettering layer with highconcentration. The dicing damaged layer on the side surface showed aconcentration distribution curve similar to that of the grinding damagedlayer. Therefore, it can also be said that the depth of the getteringlayer and the average depth of the dicing damaged layer produced duringdicing are virtually the same.

Moreover, since gettering layers are formed on both backsides and sidesurfaces of chips after dicing, laser beam irradiation for forming thefirst gettering layer can be omitted, or only the first gettering layercan be formed. Formation processes of the first gettering layer and thesecond gettering layer can be regarded as independent processes.Therefore, it is possible to provide only the first gettering layer,only the second gettering layer or both first and second getteringlayers.

Thereafter, a chip was adhered to a lead frame with LOC tape and thenbaked for 30 minutes at 150 degrees centigrade and 90 minutes at 230degrees centigrade. After the baking, wires were bonded at 150 degreescentigrade and the chip was put into a metal cavity kept at hightemperature of 180 degrees centigrade. Subsequently, resin was pouredinto the cavity. Because resin used here is thermosetting resin,temperature of 180 degrees centigrade was high enough to fully solidifythe resin. After the resin is solidified, the assembly processes of asemiconductor device are completed.

FIG. 11 shows refresh characteristic deterioration rates of DRAMs as anexample of semiconductor devices having the gettering layers in thepresent invention. FIG. 11 shows a chip as a conventional device havingno gettering layer, and (a) a result of the case where laser beam wasirradiated as the method of making the first gettering layer, as thepresent invention, and (b) a result of the case where the backside ofthe chip was pressed against a hot material as the method of making thesecond gettering layer, as the present invention, and (c) a result ofthe case where laser beam was irradiated and the chip was pressedagainst a hot material as the method of making both the first and secondgettering layers, as the present invention, respectively. Thedeterioration rate of conventional device was about 3% and those of thepresent invention were reduced to 0.5% or lower. It Is the mosteffective case to carry out both laser beam irradiation and pressing ofthe chip against a hot material, and, in this case, the deteriorationrate thereof was reduced to as low as 0.2%. The second most effectivecase was where the chip was pressed against a hot material. In thiscase, the deterioration rate thereof was 0.3%. In the case of laserirradiation, the deterioration rate was 0.5%. Accordingly, by forming agettering layer serving as a trapping site of contaminating metals, itbecomes possible to prevent characteristic deterioration due to metalliccontamination which was occurred during backside grinding and packageassembly.

In this embodiment, oxygen was used as an impurity which forms agettering layer. However, the impurity may be any of oxygen, argon,carbon, nitrogen, boron, phosphorous, arsenic, antimony and the like ora chemical compound thereof, as long as it generates dislocations orstacking faults in the crystal of a grinding damaged layer by applyingthermal treatment. However, oxygen, argon, carbon, and nitrogen arepreferred as they only require easy-to-use for an apparatus for forminga gettering layer.

In this embodiment, after backside grinding, the first gettering layerwas formed in the backside of a wafer, and the second gettering layerswere formed on both backside and side surfaces of each chip, allowingthe gettering layers to serve as trapping sites of metalliccontamination after the backside grinding process in the assemblyflowchart. As a result, even where metallic contamination occurs duringbackside grinding and package assembly, the above-mentioned trappingsites of metallic contamination, formed by thermal process in theassembly processes, does not allow the metal contamination to reachelectronic devices formed in the main surface of the substrate.Therefore, it becomes possible to prevent characteristic deteriorationdue to metallic contamination which is introduced in backside grindingand package assembly.

Embodiment 2

Next, embodiment 2 in the present invention is detailed using FBGAassembly of a semiconductor device shown in FIGS. 12 to 14 as anexample.

First of all, as shown in the assembly flowchart of FIG. 12, the surfaceof a silicon wafer on which semiconductor devices are fabricated in anormal method, was protected by a protection sheet, and the backside ofthe wafer was grinded in that state. During this grinding process, thefirst rough grinding is performed at roughness of about #300 until thethickness of the wafer becomes about 750 μm and 200 μm, and finishinggrinding was then performed at roughness of about #2000 until thethickness of the wafer becomes 180 μm. Here, a comparison is made amonga case of grinding using a normal backside grinder, and the followingcases in the present invention:

-   -   a case (d) where the backside is grinded with        copper-contamination-free transfer system, grinding blade and        grinding water;    -   a case (e) where the final grinding in the grinding process was        carried out using a copper-free adhesive for bonding a grinding        blade and a grinding wheel; and    -   a case (f) where copper on a grinded surface was cleaned before        the respective grinding processes and a copper-free adhesive was        used for bonding a grinding blade and a grinding wheel.

Since no consideration had been given to the issue of coppercontamination, conventional grinding process is carried out. So grindingprocess in this invention is carried out in a state where a transfersystem, a grinding blade and grinding water are all copper-free. Anadhesive used for bonding a grinding blade and a grinding wheel usuallycontains several 10% of copper to enhance its adhesive force, and agrinding damaged layer after finishing grinding contains copper of about1×10¹²/cm³. As shown in FIG. 13, a copper concentration in conventionalprocess was as high as about 1×10¹⁷/cm³ near the surface of a grindingdamaged layer. Meanwhile, in the case where a copper-free adhesive (withcopper concentration of 1% or lower) is used, a grinding damaged layercontains copper of less than 1×10¹¹/cm³, and the concentration of coppernear the surface is 1×10¹⁶/cm³ or lower with some variations dependingon each grinding. In addition, since copper is introduced into agrinding damaged layer while damages were formed during grindingprocess, the copper contamination may be generated through a transfersystem or the like even if the above-mentioned adhesive contains nocopper. Hence, if copper contamination is cleaned before grinding, itbecomes more effective to use a copper-free adhesive. Here, coppercontamination was cleaned with pure water cleaning only but may becleaned with diluted nitric acid. Note that the grinding damaged layercontained high concentration of oxygen (1×10¹⁸/cm³ or higher).

Next, after the wafer was diced into chips, each chip was adhered to aFBGA substrate at 180 degrees centigrade through an adhesive tape.Thereafter, wire bonding was carried out at 180 degrees centigrade andthe chips were sealed with resin, and baking is carried out 7 hours at180 degrees centigrade. Thermal process is applied to the chips manytimes at 180 degrees centigrade, and therefore, defects and scratches(cracks) are oxidized by oxygen on a grinding damaged layer, providingthe chips with gettering effect against metallic contamination. At thesame time, non-gettered contaminating metal is diffused towards the mainsurface of the substrate. Since copper is particularly quickly diffused,copper reaches the main surface first. If copper contained in a grindingdamaged layer is maintained at 1×10¹⁶/cm³ or lower as in the presentinvention, copper rarely reaches the substrate's main surface since mostcopper is gettered by the oxidized defects and scratches (cracks).Therefore, last solider balls were attached by reflowing at 250 degreescentigrade.

FIG. 14 shows refresh characteristic deterioration rates of DRAMs as anexample of semiconductor devices wherein copper concentrations of thedamaged layers are reduced, in the present invention. Where aconventional grinding process was used, deterioration rate was about 3%.Meanwhile, in a case (d) in the present invention where backsidegrinding process was carried out with copper-contamination-free transfersystem, grinding blade, grinding water and the like, a deteriorationrate was reduced as low as 1%. Furthermore, in a case (e) in the presentinvention where a grinding blade and a grinding wheel used for finishgrinding in grinding processes was bonded with a copper-free adhesive, adeterioration rate was reduced as low as 0.5%. In a case (f) in thepresent invention where copper on a grinded surface was cleaned (withwater or both diluted nitric acid and water) before the respectivegrinding processes, and a copper-free adhesive was used for bonding agrinding blade and a grinding wheel, the deterioration rate was reducedas low as about 0.3%. It is obvious that a combination of thisembodiment and foregoing embodiment 1 reduces the deterioration ratefurther.

Embodiment 2 shows that special thermal treatment is not applied to agrinding damaged layer by using no contaminating metal during assemblyprocesses and removing the contaminating metal by cleaning in order toprevent characteristic deterioration of a semiconductor device. In thepresent invention, copper used in an adhesive for bonding a grindingblade and a grinding wheel was described as a representative ofcontaminating metals. However, other metals, such as iron, nickel,chromium and the like that are often used in fabrication apparatuses ofsemiconductor devices, cause characteristic deterioration ofsemiconductor devices. Therefore, needless to say, the concentrationrates of such metals should also be maintained at 1×10¹⁸/cm³ or lower.

Embodiment 3

Next, embodiment 3 of the present invention is detailed. In thisExample, the gettering layer described in embodiment 1 was formed by aplasma treatment.

In the flowchart of FIG. 15, similarly to embodiment 1, a firstgettering layer was formed on the backside of a wafer by a first plasmatreatment after backside of the wafer was grinded, and then a secondgettering layer was formed by a second plasma treatment after the waferis diced. Both the first and second plasma treatments are carried out ina plasma atmosphere containing an impurity. These plasma treatments wereperformed, for example, using a plasma device, with plasma power of 2KW, at substrate temperature of 150 degrees centigrade, using diluentgas containing oxygen as an impurity, at pressure of 1 Torr, and fortreatment time of 60 seconds. Processes of backside grinding, dicing,bonding chips to LOC tape, wire bonding, and resin sealing are the sameas those of embodiment 1 and descriptions thereof are thus omitted.

In case of the plasma treatment, a gettering layer can be formed even atlow temperature such as 150 degrees centigrade as described above. Thistemperature is even lower than that for an assembly process (bakingtemperature after bonding of chips and LOC tape is 230 degreescentigrade) and does not cause hydrogen desorption of a passivation filmwhich protects the surface of a semiconductor device. Therefore, thistemperature has the advantage which allows to make a plasma treatmenttime to be carried out for extended time and to obtain a highconcentration of introduced impurity. Further, since the treatmenttemperature is lower than heat-resistance temperature of a protectionsheet for dicing, the plasma treatment can be conducted, while using theprotection sheet. Therefore, this is advantageous in that freelytransferring and handling of wafers in manufacturing processes can bedone more freely.

FIG. 16 shows a refresh characteristic deterioration rate of a DRAMwhich is as a novel semiconductor device in case (g) where only thesecond gettering layer was formed by the second plasma treatment in thepresent embodiment. A deterioration rate in conventional device withoutany gettering layer is not formed was about 3%, whereas thedeterioration rate of this embodiment was reduced as low as 0.3%. Inaddition, oxygen concentration near the backside surface and at anaverage depth of the grinding damaged layer are 2×10²¹/cm³ and2×10¹⁹/cm³, respectively, in the same way as the case in embodiment 1where a chip was pressed against a hot material (see FIG. 8). Formationof the first gettering layer by the first plasma treatment and formationof the second gettering layer by the second plasma treatment wereindependently processed, respectively. Therefore, it is possible toprovide only the first gettering layer, only the second gettering layer,or both of the first and second gettering layers.

The preferred conditions for the plasma treatment are that an impurityshould be containing any of oxygen, argon, carbon, boron, phosphorous,arsenic, antimony, or a compound thereof, the substrate temperatureshould be between 100 and 500 degrees centigrade, the plasma power ofbetween 1 and 5 KW, the pressure of between 1 and 10 Torr, and thetreatment time of between 0.1 and 200 seconds. In addition, thesubstrate temperature within the range of between 100 and 300 degreescentigrade is more preferred since there is less affections of hydrogendesorption at this range of temperature.

Similarly to example 1, after backside grinding, the first getteringlayer was formed in the backside of a wafer, and the second getteringlayer were formed in both backside and side surfaces of each chip,allowing the gettering layers to serve as trapping sites of metalliccontamination after the backside grinding process in the assemblyflowchart. As a result, even where metallic contamination was occurredon backside grinding and package assembly, the above-mentioned trappingsites of metallic contamination, formed by thermal loading in theassembly processes, does not allow the metal contamination to reachelectronic devices formed in the main surface of the substrate.Therefore, it becomes possible to prevent characteristic deteriorationdue to metallic contamination which is generated in backside grindingand package assembly.

The present invention is described specifically based on embodiments.However, needless to say, the present invention is not limited to theseembodiments and may be modified in varying manners not departing fromthe gist thereof.

1. A semiconductor device on which a backside grinded chip is mounted,wherein the device comprises a gettering layer obtained by an impurityto a backside of the chip.
 2. A semiconductor device according to claim1, further comprising a gettering layer on a side surface of the chip byintroducing an impurity.
 3. A semiconductor device according to claim 1,wherein a depth of the gettering layer is virtually the same as anaverage depth of a damaged layer.
 4. A semiconductor device according toclaim 1, wherein the impurity contains any of oxygen, argon, carbon,nitrogen, boron, phosphorous, arsenic, antimony, or a chemical compoundthereof.
 5. A semiconductor device according to claim 4, wherein anoxygen concentration at the depth of the gettering layer is 1×10 ¹⁹/cm³or higher but not exceeding 1×10²²/cm³.
 6. A semiconductor deviceaccording to claim 1, wherein a maximum metal concentration within thegettering layer is 1×10¹⁸/cm³ or lower.
 7. A manufacturing method of asemiconductor device, comprising: a backside grinding step; and a firstgettering step for forming a first gettering layer on a backside of awafer which is backside-grinded in the backside grinding step, wherein,in the first gettering step, the first gettering layer is formed byintroducing an impurity into the backside of the wafer.
 8. Amanufacturing method of a semiconductor device wherein, in the firstgettering step according to claim 7, the first gettering layer is formedby applying a thermal treatment to the grinded backside of the wafer inan atmosphere containing an impurity at backside temperature rangingfrom 300 to 900 degrees centigrade with treatment time of 0.01 secondsor longer but not exceeding 10 seconds.
 9. A manufacturing method of asemiconductor device, wherein the thermal treatment according to claim 8is a treatment for irradiating laser beam irradiation to the backside ofthe chip.
 10. A manufacturing method of a semiconductor device wherein,in the first gettering step according to claim 7, the first getteringlayer is formed by applying plasma treatment to the grinded backside ofthe wafer in an atmosphere containing the impurity at backsidetemperature ranging from 100 to 500 degrees centigrade with treatmenttime of 0.1 seconds or longer but not exceeding 100 seconds.
 11. Amanufacturing method of a semiconductor device, wherein the impurityaccording to the claim 7 contains any of oxygen, argon, carbon,nitrogen, boron, phosphorous, arsenic, antimony, or a chemical compoundthereof.
 12. A manufacturing method of a semiconductor device,comprising: a backside grinding step: a dicing step; and a secondgettering step for forming second gettering layers on backside and sidesurface of a diced chip, wherein, in the second gettering step, thesecond gettering layers are formed by introducing an impurity to thebackside and side surface of the chip.
 13. A manufacturing method of asemiconductor device wherein, in the second gettering step according toclaim 12, the second gettering layers are formed by applying a thermaltreatment to the backside and side surface of the chip in an atmospherecontaining an impurity at backside temperature ranging from 300 to 900degrees centigrade with treatment time of 0.01 second or longer but notexceeding 10 seconds.
 14. A manufacturing method of a semiconductordevice, wherein the thermal treatment according to claim 13 is performedby pressing the backside of the chip against a hot material.
 15. Amanufacturing method of a semiconductor device wherein, in the secondgettering step of claim 12, the second gettering layers are formed byapplying plasma treatment to the backside and side surface of the chipin an atmosphere containing the impurity at backside temperature rangingfrom 100 to 500 degrees centigrade with treatment time of 0.1 seconds orlonger but not exceeding 100 seconds.
 16. A manufacturing method of asemiconductor device, wherein the impurity according to claim 12contains any of oxygen, argon, carbon, nitrogen, boron, phosphorous,arsenic, antimony, or a chemical compound thereof.
 17. A manufacturingmethod of a semiconductor device, comprising; the backside grinding stepaccording to claim 7 for performing grinding in the state where there isno metallic contamination of a transportation system, a grinding bladeand grinding water used for a grinding apparatus.
 18. A manufacturingmethod of a semiconductor device, comprising; the backside grinding stepaccording to claim 7 for performing at least last grinding in thegrinding processes in the state of using a copper-free adhesive forbonding a grinding blade and a grinding wheel.
 19. A manufacturingmethod of a semiconductor device, comprising; the backside grinding stepaccording to claim 7 for bonding a grinding blade and a grinding wheelin the state of using a copper-free adhesive, after cleaning to removecopper on a grinded surface prior to each grinding in a plurality ofgrinding processes.